1. Field of the Invention
The present invention relates to an apparatus for transferring blocks of image data.
2. Description of the Prior Art
In usual bit map display systems, one frame of image data is written into a frame buffer (FB) memory which comprises a dynamic RAM, and the image data are successively read from the frame buffer memory and supplied to a display unit such as a CRT, which displays on its display screen an image represented by the image data. The displayed image is made up of a plurality of picture elements or pixels corresponding respectively to the image data which are stored at respective addresses of the frame buffer memory.
CRTs for use as graphic display terminals in CAD, CAM, and other similar applications have high resolutions, for example, of 1280.times.1024 dots. When such a CRT is scanned by the noninterlacing scanning process at a frequency of 60 Hz, a dot clock signal used to read one dot pixel from the frame buffer memory is required to have a frequency in excess of 100 MHz (i.e., a period in excess of 10 ns). However, since the dynamic RAM used as the frame buffer memory can be accessed at a speed which is much lower than the above frequency, it is customary practice to access a plurality of dynamic RAM chips simultaneously in one access cycle for reading image data representing plural dots at one time.
The image data of plural dots which have simultaneously been read are then supplied to a high-speed shift register. The image data stored in the shift register are successively read with the dot clock signal and supplied to the CRT. In this manner, the low access speed of the dynamic RAM is compensated for.
In view of recent microprocessors available with wider buses, it has become possible to write image data representing plural dots simultaneously into a frame buffer memory. The image data stored in the frame buffer memory are allotted addresses such that a group of image data representing plural dots corresponds to one address. It is customary to group a horizontal array of successive pixels, the number of which is represented by a power of 2. For example, one address is assigned to each horizontal array of successive pixels that represent 16 dots.
FIG. 1 of the accompanying drawings shows a structure of image data stored in a frame buffer memory, the image data being divided into groups of pixels representing 16 dots. In the frame buffer memory, a plurality of one-dot image data 1 are arranged in horizontal and vertical directions (indicated respectively by the arrows X and Y) which correspond to those on a display screen. The image data 1 are divided in the horizontal direction into pixel blocks 2A, 2B, 2C, . . . each composed of 16 pixels or dots. In each of the pixel blocks 2A, 2B, 2C, . . . , the image data which are 16 dots long in the horizontal direction and one dot long in the vertical direction are allotted one address. Therefore, the groups or units of image data which are 16 dots long in the horizontal direction and one dot long in the vertical direction are written into and read out of the frame buffer memory, one at a time.
It is assumed that image data representing a plurality of dots are to be transferred from one address region to another address region for translating a displayed image of an object on a display screen. If the address region from which the image data are to be transferred, i.e., the source address region, adjoins the boundaries of a pixel block composed of 16 pixels, and the address region to which the image data are to be transferred, the destination address region, adjoins the boundaries of another pixel block, then the image data can easily be transferred. Such a transfer of the image data can be carried out by reading one pixel block, writing one pixel block, reading one pixel block, . . . , reading one pixel block, and writing one pixel block.
More specifically, image data 3 (FIG. 1) corresponding to 16.times.2 dots can be transferred from an address region P1 adjoining the boundaries of the pixel block 2A to an address region P2 adjoining the boundaries of the pixel block 2B simply by reading and writing image data corresponding to 16 dots in two repetitive cycles.
However, if image data are to be transferred from or to an address region which does not adjoin a pixel block, then the process of transferring the image data is much more complex.
Specifically, as shown in in FIG. 1, it is assumed that image data 4 are to be transferred, from the righthand to the lefthand end of an address region P3, to an address region P4. Image data 5B in the source address region P3 within the pixel block 2B are three dots long in the horizontal direction, whereas image data 6A in the destination address region P4 within the pixel block 2C are nine dots long in the horizontal direction. The image data (including the image data 5B) in the pixel block 2B and the image data 5A in the pixel block 2A are pre-read from the source address region P3, and image data (including the image data 6A) produced by processing the two image data groups thus pre-read are written into the pixel block 2C in the destination address region P4.
Image data 6B at the lefthand end of the destination address region P4 are one dot long in the horizontal direction. Since the image data 6B have already been pre-read from the source address region P3, the step of reading the image data again may possibly be omitted. For the transfer of image data irrespective of the boundaries of the pixel blocks, as described above, the transfer procedure (transfer efficiency) may be optimized for an increased transfer rate by employing the pre-reading process or the like. Heretofore, no consideration has been given to optimization of the transfer efficiency.